1. Field of the Invention
The present invention relates to a self refresh circuit for a semiconductor memory device, and in particular to an improved self refresh circuit for a semiconductor memory device which can reduce power consumption by varying a self refresh period according to a data holding time of a cell which is a function of temperature.
2. General Background and Related Art
In general, a DRAM cell consists of an NMOS transistor serving as a switch and a capacitor for storing electric charges which represent data. For example, binary information 0 or 1 can be represented by the terminal voltage of the capacitor. A high terminal voltage could represent a 1 and a low terminal voltage could represent a 0 or the opposite could be the case. A so-called xe2x80x9cwritexe2x80x9d operation occurs when a voltage corresponding to the binary information is applied to the memory cell. A so-called xe2x80x9creadxe2x80x9d operation occurs when the existence or absence of a capacitor charge is determined by sensing terminal voltage of the capacitor and providing a signal indicative thereof.
Generally speaking, holding data in the cell should not require consumption of power because the capacitor is merely storing a charge. However, a charge being held by a capacitor gradually reduces due to a leakage current through the PN junction of the MOS transistor, and thus the data will eventually be lost unless it is refreshed. To refresh the data, it is necessary to read the data in the memory cell and then re-charge the capacitor accordingly. This refresh operation must be periodically repeated to prevent data from degenerating. The refresh period required is related to the process and structure of the capacitor. The data is maintained according to a dynamic process, such as a repeated refresh operation.
The refresh operation is performed by enabling a word line according to a row address, and enabling a sense amplifier (hereinafter xe2x80x9csense ampxe2x80x9d). In addition, the refresh operating may be carried out by operating the sense amp, without receiving refresh address. I this case, the refresh address counter embedded in a DRAM chip, generates a row address.
xe2x80x9cRefreshxe2x80x9d operations can be further categorized as xe2x80x9cauto-refreshxe2x80x9d and xe2x80x9cself refreshxe2x80x9d. An auto-refresh operation occurs when, during operation of the chip, there is periodically generated and received a refresh command. During this auto-refresh, other commands to the chip are intercepted, refresh is carried out, and then the chip is allowed to receive and act on the other commands. For self-refresh there is established a regular periodic reading of cell data and re-writing that data in order to prevent a data loss even when the chip is operating in a so-called standby mode. An internal timer controls the frequency of self-refresh.
Self refresh is used for low power operation of the chip and to store data for an extended period of time. In self refresh operation, when entire banks are in an idle state, a chip selection signal /CS, a RAS bar signal /RAS, a CAS bar signal /CAS and a clock enable signal CKE are low, and a write enable signal /WE is high, thereby initiating self refresh mode operation. Once the self refresh mode is enabled, all input pins except for a clock enable pin are ignored.
In order to stop the self refresh operation, when a clock buffer is operated by receiving a clock signal clk and converting the clock enable signal CKE to a high level, the SDRAM is in the idle state after a predetermined time tRC. At this time, other commands can be input.
FIG. 1 (Prior Art) is a block diagram illustrating a conventional self refresh circuit. The conventional self refresh circuit includes a self-refresh command decoder 10, a self refresh generating unit 20, a ring oscillator unit 30, a frequency driver unit 40, a self refresh request circuit unit 50, a RAS generating unit 60 and a predecoder unit 70.
Firstly, when an output signal from self refresh command decoder 10 is input to the self refresh generating unit 20, the self refresh generating unit 20 outputs a signal srefz for enabling the self refresh mode to the ring oscillator unit 30. According to convention, the signal srefz is enabled when it is high.
The ring oscillator unit 30 outputs a pulse signal toggled in a period of 1 xcexcs to the frequency driver unit 40 according to the signal srefz from the self refresh generating unit 20. The frequency driver unit 40 receives the pulse signal from the ring oscillator unit 30, and generates a pulse signal having a double period. Here, the pulse signal is a refresh time request signal output to the self refresh request unit 50.
The self refresh request unit 50 selects and outputs a refresh period signal (generally 8 xcexcs, 16 xcexcs) suitable for a data holding time and a refresh cycle of the DRAM cell in accordance with the refresh time request signal from the frequency driver unit 40. The RAS generating unit 60 generates the RAS signal according to the refresh period signal from the self refresh request unit 50. The predecoder unit 70 is operated according to the RAS signal.
Although not illustrated, a decoder circuit and a word line driving circuit are operated by the predecoder unit 70, thereby performing the self refresh operation.
FIG. 2 (Prior Art) is a graph showing variations of a required self refresh period as a function of temperature. When temperature increases, the required self refresh period is reduced. Conversely, when temperature decreases, the required self refresh period is increased. Since the data holding time of the DRAM cell varies according to temperature, the self refresh period is inversely proportional to temperature. In general, when the temperature increases by 10xc2x0 C., the data holding time of the cell is reduced into a half.
However, the conventional self refresh circuit is designed to have a predetermined self refresh period, without being able to adjust for variations of the data holding time of the DRAM cell which fluctuate with temperature. That is, the conventional self refresh circuit is designed to have a constant self refresh period based on presumed worst conditions, which results in increased power consumption.
Accordingly, the claimed inventions feature, at least in part, a self refresh circuit for a semiconductor memory device which can reduce power consumption by varying a self refresh period according to a data holding time of a cell that is a function of temperature.
There is provided a self refresh circuit for a semiconductor memory device, including a temperature sensing unit for sensing a temperature, and generating a bias current for adjusting a self refresh period according to a data holding time of a memory cell that is a function of temperature. A ring oscillator unit generates a pulse signal having a period actively varied according to the temperature by the bias current from the temperature sensing unit.
The temperature sensing unit includes a first reference voltage generating unit for generating a reference voltage that is inversely proportional to temperature variations. A second reference voltage generating unit receives the output signal from the first reference voltage generating unit, and generates a reference voltage that is proportional to temperature variations. A third reference voltage generating unit receives the output signal from the second reference voltage generating unit, and generates a current for controlling the operation of the ring oscillator unit. The operation of the ring oscillator unit is controlled according to the output signals from the second and third reference voltage generating units.
The first reference voltage generating unit includes a PMOS transistor connected between a power supply voltage node and an output terminal in a diode structure. Two NMOS transistors are connected in series between the output terminal and a ground voltage node in a diode structure.
The second reference voltage generating unit includes a PMOS transistor connected between the power supply voltage node and an output terminal in a diode structure. An NMOS transistor is connected between the output terminal and the ground voltage node, and has its gate connected to receive the output signal from the first reference voltage generating unit.
The third reference voltage generating unit includes a PMOS transistor connected between the power supply voltage node and an output terminal in a diode structure. An NMOS transistor is connected between the output terminal and the ground voltage node, and has its gate connected to receive the output signal from the second reference voltage generating unit.